1. Field of the Invention
The present invention relates to an electrostatic protection circuit for protecting a semiconductor device so as not to destroy it in the case where a surge due to electro static discharge (ESD) from outside (hereafter, referred to as electrostatic surge) flows into the semiconductor device.
2. Description of Related Art
In recent years, higher integration of a semiconductor device has been promoted by progress in semiconductor technology, and the semiconductor device is consequently becoming more vulnerable to destruction of a gate insulator and the like by electrostatic surge. To be more specific, there has been a higher possibility that elements in an input-output circuit and an internal circuit configuring the semiconductor device are destroyed or performance thereof is lowered by the electrostatic surge infiltrating in the semiconductor device from an external connection input-output pad (hereafter, referred to as an I/O terminal). For that reason, there is provided an electrostatic protection circuit for protecting the input-output circuit and internal circuit in the semiconductor device from the electrostatic surge. Such an electrostatic protection circuit is intended to prevent a situation in an manufacturing process of the semiconductor device where, on contacting the I/O terminal with a part of a human body or equipment, static electricity is instantaneously accumulated in the input-output circuit and a surge current passes based on stored charge thereof to lead to destruction of the elements in the input-output circuit and internal circuit.
Thus, when the electrostatic surge is inputted, the charge rapidly accumulated in the input-output circuit is dissipated by using the protection circuit so as to discharge the electrostatic surge. Such an ESD protection circuit may also be provided in the input-output circuit of the semiconductor device.
As a method for protecting the internal circuit when the electrostatic surge is inputted to the I/O terminal, there is a proposed method of using a grounded gate NMOSFET (referred to as GGNMOS) and a source connected gate PMOSFET (referred to as SGPMOS).
For instance, the ESD protection circuit using the GGNMOS and SGPMOS is shown in FIG. 2 of U.S. Pat. No. 6,765,772. Reference characters M20A and M21A of FIG. 2 denote the GGNMOS, and M20B and M21B denote the SGPMOS.
As for the GGNMOS and SGPMOS, a gate terminal is connected to a source terminal and a substrate terminal, and MOSFET operation is in an off state. When the electrostatic surge is applied to drain terminals of the GGNMOS and SGPMOS, the MOSFET operation remains off. However, a parasitic bipolar junction transistor (referred to as a parasitic BJT) is turned on between a collector and an emitter (that is, between a drain and a source) to have the electrostatic surge discharged. The parasitic BJT is parasitic on an MOSFET while rendering the drain terminal as a collector terminal, the source terminal as an emitter terminal and the substrate terminal as a base terminal.
A principle of operation of the parasitic BJT of the GGNMOS and SGPMOS is as follows. First, a high voltage is generated by the electrostatic surge in a junction of the drain. It causes a junction breakdown so that a current passes between the drain and the substrate. As the base of the BJT is connected to the substrate terminal via a relatively high-resistance well area, the base is biased by an IR voltage drop. As the base is biased, the BJT is turned on between the collector and the emitter to have the electrostatic surge discharged.
In the case of using the GGNMOS and SGPMOS for ESD protection on an input-output buffer, the MOSFETs for the output buffer are connected in parallel with the GGNMOS and SGPMOS as shown in FIG. 2 of U.S. Pat. No. 6,765,772. As for the MOSFETs for the output buffer, reference characters M22A and M23A of FIG. 2 denote buffer NMOSFETs for pull-down, and M22B and M23B denote buffer PMOSFETs for pull-up.
When the electrostatic surge is applied to the I/O terminal, an electric potential of the gate of the MOSFET for the output buffer may be the electric potential for turning on as the operation of the MOSFET.
Thought is given, by way of example, to the case where the electrostatic surge of positive polarity is applied to the I/O terminal with a low-level side power supply terminal (hereafter, referred to as a V SS terminal) as a reference potential. The I/O terminal has the buffer PMOSFET and SGPMOS connected thereto. As a PN junction diode is parasitic between the drain and the substrate of the buffer PMOSFET and SGPMOS, a high-level side power supply terminal (hereafter, referred to as a V DD terminal) connected to the substrate terminal is boosted to a positive potential to be conducting from the I/O terminal to the substrate via the PN junction diode. For that reason, a logic circuit for controlling an output buffer is in an operable state when applying the electrostatic surge. The electric potential of a control signal of the logic circuit is indefinite, and there may be the cases where a gate potential of the output buffer becomes on depending on a configuration of the logic circuit.
In the case where the drain of the MOSFET for the output buffer is boosted by the electrostatic surge at the potential for turning on the gate, the parasitic BJT of the MOSFET for the output buffer is turned on at a lower drain voltage than the GGNMOS and SGPMOS of the potential at which the gate is off. This is because a drain current of the MOSFET for the output buffer which is reversing is superimposed on an emitter current of the parasitic BJT.
Thus, in the case where the MOSFET for the output buffer of the potential for turning on the gate operates as a discharge device at a lower potential than the potential at which the GGNMOS and SGPMOS operate as discharge devices, it is feared that the currents gather on the MOSFET for the output buffer and a sufficient withstand voltage cannot be secured by the MOSFET for the output buffer so as to lead to destruction.
As measures against the fear, there is a proposal of a circuit and a method as shown in FIG. 3 of U.S. Pat. No. 6,765,772. The measures and method of a similar concept are disclosed in US Patent Application Laid-Open No. 2004/0105201 A1. When a potential V cc of the V DD terminal is boosted by the electrostatic surge, an input terminal of a switching circuit 46 is boosted via a diode string denoted by a reference numeral 44, and the gates of the buffer NMOSFETs (M52A, M53A) are fixed at a low level via a driving circuit 48 to turn off the buffer NMOSFETs.
On normal operation, the input terminal of the switching circuit 46 is at a potential lower than the potential V cc by a potential of a turn-on voltage 0.7 V of the diode □ [number of stages of a diode string 44]. It is set up to be at a potential below a circuit threshold of the switching circuit 46 by adjusting the number of stages of the diode string 44 so as not to influence circuit operation of an I/O buffer circuit 50.
In the case of using the circuit proposed by U.S. Pat. No. 6,765,772, however, there is no circuit for lowering the potential when the potential of a node as an output terminal of the diode string 44 and the input terminal of the switching circuit 46 is boosted due to influence of noise and the like. Therefore, there is a danger that the circuit may malfunction. As a measure for avoiding this danger, there is a thinkable method of inserting a resistance between the node and the ground terminal as indicated in claim 13 of US Patent Application Laid-Open No. 2004/0105201 A1. In the case of taking such a measure, however, it is necessary to boost the potential of the node as the input terminal of the switching circuit 46 by passing a current through the resistance and causing the IR voltage drop in order to operate the switching circuit 46 when the electrostatic surge is applied. For that reason, a sufficiently large current should be passed through the diode string 44, and the potential V cc of the V DD terminal needs to be sufficiently boosted for that purpose. Nevertheless, an allowable maximum value of V cc is the voltage at which the parasitic BJT of the MOSFET for the output buffer is turned on, and it is necessary to work out a design so that the switching circuit 46 operates at a lower voltage than that. For this reason, a method of reducing the number of stages of the diode string 44 is thinkable as the method of lowering the voltage. In that case, however, a both-end voltage of the resistance increases and a leakage current between V cc and the ground increases so that wasteful power consumption increases. Therefore, there is a limit to a design margin for simultaneously satisfying a specification of a required leakage current and a specification of the value of V cc for operating the switching circuit 46 when the electrostatic surge is applied. There are the cases where both cannot be satisfied in some cases.